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Embedded Systems Development and Labs; The English Edition
PUPC access address: 0X01D20018
PCONC reset value: 0X0FF0FFFF
Table 4-15 Port D
Port D Pin function Port D Pin function Port D Pin function
PD0 VD0 PD3 VD3 PD6 VM
PD1 VD1 PD4 VCLK PD7 VFRAME
PD2 VD2 PD5 VLINE
PCOND access address: 0X01D2001C
PDATD access address: 0X01D20020
PUPD access address: 0X01D20024
PCOND reset value: 0XAAAA
Table 4-16 Port E
Port E Pin function Port E Pin function Port E Pin function
PE0 OUTPUT(LCD) PE3 RESERVE PE6 OUTPUT(TSP)
PE1 TXD0 PE4 OUTPUT(TSP) PE7 OUTPUT(TSP)
PE2 RXD0 PE5 OUTPUT(TSP) PE8 CODECLK
PCONE access address: 0X01D20028
PDATE access address: 0X01D2002C
PUPE access address: 0X01D20030
PCONE reset value: 0X25529
Table 4-17 Port F
Port F Pin function Port F Pin function Port F Pin function
PF0 IICSCL PF3 IN(Nand Flash) PF6 out(Nand Flash)
PF1 IICSDA PF4 out(Nand Flash) PF7 IN(bootloader)
PF2 RESERVED PF5 out(Nand Flash) PF8 IN(bootloader)
PCONF access address: 0X01D20034
PDATF access address: 0X01D20038
PUPF access address: 0X01D2003C
PCONF reset value: 0X00252A
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Table 4-18 Port G
Port G Pin function Port G Pin function Port G Pin function
PG0 EXINT0 PG3 EXINT3 PG6 EXINT6
PG1 EXINT1 PG4 EXINT4 PG7 EXINT7
PG2 EXINT2 PG5 EXINT5
PCONG access address: 0X01D20040
PDATG access address: 0X01D20044
PUPG access address: 0X01D20048
PCONG reset value: 0XFFFF
2. The Description of the Circuit
In Table 4-13 PB9 and PB10 pins are defined as outputs and are connected to LED1 and LED2. Figure 4-5
shows the circuit connections for the LED1 and LED2. The anodes of LED1 and LED2 are connected to the pin
47 of S3C44B0X which is VDD33. VDD33 pin provides a 3.3V dc voltage. The cathodes of LED1 and LED2
are connected to pin 23 (PB9) and 24 (PB10), respectively. These two pins belong to Port B and have been
configured as outputs. Writing a 1 or a 0 to the specific bit of the PDATAB register can make the pin’s output
low or high. When the pin 23, 24 is low, the LEDs will be on (lit). When the pin 23, 24 is high, the LEDs will be
off.
LED1
23 R95
NGCS4
24 R96
NGCS5
S3C44B0X LED2
47
VDD33
Figure 4-5. Connection diagram to LED 1 and LED 2
4.2.5 Operation Steps
1) Prepare the Lab environment. Connect the Embest Emulator to the target board. Connect the target board
UART0 to the PC serial port through the serial cable provided by the Embest development system.
2) Run the PC Hyper Terminal (set to 115200 bits per second, 8 data bits, none parity, 1 stop bits, none flow
control).
3) Connect the Embest Emulator to the target board. Open the LED_test.ews project file that is located in
the …\EmbestIDE\Examples\Samsung\S3CEV40 directory. Compile and link the project. Connect to the target
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board and download the program.
NOTE: please note that the debug window should be set as in Figure 4-5a:
Figure 4-5a. Debug settings for the project
4) Watch the hyper terminal output. The following should be displayed:
Embest 44B0X Evaluation Board (S3CEV40)
LED Test Example
5) The LED1 and LED2 will be in the following states:
LED1 on Æ LED2 on Æ LED1 and LED2 onÆ LED2 off Æ LED1 off.
4.2.6 Sample Programs
/*****************************************************************************
* File Name: light.c
* Author: embest
* Description: control board's two LEDs on or offf
* History:
*****************************************************************************/
/*--- include files ---*/
#include "44b.h"
#include "44blib.h"
/*--- global variables ---*/
int led_state; /* LED status */
/*--- function declare ---*/
void Led_Test(); /* LED test */
void leds_on(); /* all leds on */
void leds_off(); /* all leds off */
void led1_on(); /* led 1 on */
void led1_off(); /* led 1 off */
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void led2_on(); /* led 2 on */
void led2_off(); /* led 2 off */
//void Led_Display(int LedStatus); /* led control */
/*--- function code---*/
/*************************************************************************
* name: Led_Test
* func: leds test funciton
* para: none
* ret: none
* modify:
* comment:
**************************************************************************/
void Led_Test()
{
/* 1 on -> 2 on -> all on -> 2 off -> 1 off */
leds_off();
Delay(1000);
led1_on();
Delay(1000);
led1_off();
led2_on();
Delay(1000);
leds_on();
Delay(1000);
led2_off();
Delay(1000);
led1_off();
}
/***************************************************************************
* name: leds_on
* func: all leds on
* para: none
* ret: none
* modify:
* comment:
***************************************************************************/
void leds_on()
{
Led_Display(0x3);
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}
/**************************************************************************
* name: leds_off
* func: all leds off
* para: none
* ret: none
* modify:
* comment:
*****************************************************************************/
void leds_off()
{
Led_Display(0x0);
}
/****************************************************************************
* name: led1_on
* func: led 1 on
* para: none
* ret: none
* modify:
* comment:
*****************************************************************************/
void led1_on()
{
led_state = led_state | 0x1;
Led_Display(led_state);
}
/*****************************************************************************
* name: led1_off
* func: led 1 off
* para: none
* ret: none
* modify:
* comment:
****************************************************************************/
void led1_off()
{
led_state = led_state & 0xfe;
Led_Display(led_state);
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}
/*****************************************************************************
* name: led2_on
* func: led 2 on
* para: none
* ret: none
* modify:
* comment:
******************************************************************************/
void led2_on()
{
led_state = led_state | 0x2;
Led_Display(led_state);
}
/*****************************************************************************
* name: led2_off
* func: led 2 off
* para: none
* ret: none
* modify:
* comment:
******************************************************************************/
void led2_off()
{
led_state = led_state & 0xfd;
Led_Display(led_state);
}
#define _LIB_LED_off // _LIB_LED_off -- don't use LIB settings.
#ifndef _LIB_LED_off
/**************************************************************************
* name: Led_Display
* func: Led Display control function
* para: LedStatus -- led's status
* ret: none
* modify:
* comment:
**************************************************************************/
void Led_Display(int LedStatus)
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{
led_state = LedStatus;
if((LedStatus&0x01)==0x01)
rPDATB=rPDATB&0x5ff;
else
rPDATB=rPDATB|0x200;
if((LedStatus&0x02)==0x02)
rPDATB=rPDATB&0x3ff;
else
rPDATB=rPDATB|0x400;
}
#endif
4.2.7 Exercises
Write a program to implement LED1 and LED2 display 00-11 in a loop.
4.3 Interrupt Lab
4.3.1 Purpose
● Get familiar with ARM interrupt methods and principles.
● Get familiar with the details of ISR (Interrupt Service Routine) programming in ARM based systems.
4.3.2 Lab Equipment
● Hardware: Embest S3CEV40 hardware platform, Embest Standard/Power Emulator, PC.
● Software: Embest IDE 2003, Windows 98/2000/NT/XP operation system.
4.3.3 Content of the Lab
Learn the principals of ARM interrupt system. Get familiar with S3C44B0X interrupt registers. Learn various
programming methods used in dealing with interrupts. Write programs that implement an interrupt service
routine.
● Use button SB2 to trigger the interrupt EINT6. The interrupt will turn LED1 on; then the 8-SEG LED will
display the characters 0 to F 1 time; then the LED1 will be turned off.
● Use button SB3 to trigger the interrupt EINT7. The interrupt will turn LED1 on; then the 8-SEG LED will
display the characters 0 to F 1 time; then the LED1 will be turned off.
To understand the interface to the 8-SEG LED display please refer to the “8-SEG LED Display Lab” presented
in Section 4.6.
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4.3.4 Principles of the Lab
The integrated interrupt controller of the S3C44B0X processor can process 30 interrupt requests. These
interrupt sources include internal peripherals such as the DMA controller, UART, SIO, etc. In these interrupt
sources, the four external interrupts (EINT4/5/6/7) are 'OR'ed to the interrupt controller.The UART0 and 1
Error interrupt are 'OR'ed, as well.
The role of the interrupt controller is to ask for the FIQ or IRQ interrupt request to the ARM7TDMI core after
making the arbitration process when there are multiple interrupt requests from internal peripherals and external
interrupt request pins.
Originally, ARM7TDMI core permits only the FIQ or IRQ interrupt, which is the arbitration process based on
priority by software. For example, if you define all interrupt sources as IRQ (Interrupt Mode Setting), and, if
there are 10 interrupt requests at the same time, you can determine the interrupt service priority by reading the
interrupt pending register, which indicates the type of interrupt request that will occur.
This kind of interrupt process requires a long interrupt latency until to jump to the exact service routine. (The
S3C44B0X may support this kind of interrupt processing.) To reduce the interrupt latency, S3C44B0X
microcontroller supports a new interrupt processing called vectored interrupt mode, which is a general feature
of the CISC type microcontrollers. To accomplish this, the hardware inside the S3C44B0X interrupt controller
provides the interrupt service vector directly.
When the multiple interrupt request sources are present, the hardware priority logic determines which interrupt
should be serviced. At the same time, this hardware logic applies the jump instruction of the vector table to 0x18
(or 0x1c), which performs the jump to the corresponding service routine. Compared with the previous software
method, it will reduce the interrupt latency, dramatically.
1. Interrupt Controller Operation
1) F-bit and I-bit of PSR (program status register)
If the F-bit of PSR (program status register in ARM7TDMI CPU) is set to 1, the CPU does not accept the FIQ
(fast interrupt request) from the interrupt controller. If I-bit of PSR (program status register in ARM7TDMI
CPU) is set to 1, the CPU does not accept the IRQ (interrupt request) from the interrupt controller. So, to enable
the interrupt reception, the F-bit or I-bit of PSR has to be cleared to 0 and also the corresponding bit of INTMSK
has to be cleared to 0.
2) Interrupt Mode
ARM7TDMI has 2 types of interrupt mode, FIQ or IRQ. All the interrupt sources determine the mode of
interrupt to be used at interrupt request.
3) Interrupt Pending Register
Indicates whether or not an interrupt request is pending. Whenever a pending bit is set, the interrupt service
routine starts if the I-flag or F-flag is cleared to 0. The Interrupt Pending Register is a read-only register, so the
service routine must clear the pending condition by writing a 1 to I_ISPC or F_ISPC.
4) Interrupt Mask Register
Indicates that an interrupt has been disabled if the corresponding mask bit is 1. If an interrupt mask bit of
INTMSK is 0, the interrupt will be serviced normally. If the corresponding mask bit is 1 and the interrupt is
generated, the pending bit will be set. If the global mask bit is set to 1, the interrupt pending bit will be set but all
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interrupts will not be serviced.
2. Interrupt Sources
Among 30 interrupt sources, 26 sources are provided for the interrupt controller. Four external interrupt
(EINT4/5/6/7) requests are ORed to provide a single interrupt source to the interrupt controller, and two UART
error interrupts (UERROR0/1) use the ORed configuration.
NOTE: EINT4/5/6/7 share the same interrupt request line. Therefore, the ISR (interrupt service routine) will
discriminate these four interrupt sources by reading the EXTINPHD[3:0] register. EXTINPND[3:0] must be
cleared by writing a 1 in the ISR after the corresponding ISR has been completed.
Table 4-19.
3. Vectored Interrupt Mode (Only for IRQ)
S3C44B0X has a new feature, the vectored interrupt mode, in order to reduce the interrupt latency time.
When the ARM7TDMI core receives the IRQ interrupt request from the interrupt controller, ARM7TDMI
executes the instruction located at address 0x00000018. In vectored interrupt mode, the interrupt controller will
load branch instructions on the data bus when ARM7TDMI fetches the instructions at 0x00000018. The branch
instructions let the program counter be a unique address corresponding to each interrupt source.
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The interrupt controller generates the machine code for branching to the vector address of each interrupt source.
For example, if EINT0 is IRQ, the interrupt controller must generate the branch instruction which branches to
0x20 instead of 0x18. As a result, the interrupt controller generates the machine code, 0xea000000.
The user program code must locate the branch instruction, which branches to the corresponding ISR (interrupt
service routine) at each vector address. The machine code, branch instruction, at the corresponding vector
address is calculated as follows:
Branch Instruction machine code for vectored interrupt mode = 0xea000000 +(( - address> - 0x8)>>2)
Note: A relative address must be calculated for the branch instruction.
Table 4-20 The Vector Addresses of Interrupt Sources
For example, if Timer 0 interrupt is to be processed in vector interrupt mode, the branch instruction, which
jumps to the ISR, is located at 0x00000060. The ISR start address is 0x10000. The following 32bit machine
code is written at 0x00000060. The machine code at 0x00000060 is:
0xea000000+((0x10000-0x60-0x8)>>2) = 0xea000000+0x3fe6 = 0xea003fe6
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The assembler usually generates the machine code automatically and therefore the machine code does not have
to be calculated as above.
4. Example of Vectored Interrupt Mode
In the vectored interrupt mode, CPU will branch to each interrupt address when an interrupt request is generated.
As a result, at the corresponding interrupt address there must be a branch instruction that jumps to the
corresponding ISR:
ENTRY
b ResetHandler ; 0x00
b HandlerUndef ; 0x04
b HandlerSWI ; 0x08
b HandlerPabort ; 0x0c
b HandlerDabort ; 0x10
b . ; 0x14
b HandlerIRQ ; 0x18
b HandlerFIQ ; 0x1c
ldr pc,=HandlerEINT0 ; 0x20
ldr pc,=HandlerEINT1
ldr pc,=HandlerEINT2
ldr pc,=HandlerEINT3
ldr pc,=HandlerEINT4567
ldr pc,=HandlerTICK ; 0x34
b.
b.
ldr pc,=HandlerZDMA0 ; 0x40
ldr pc,=HandlerZDMA1
ldr pc,=HandlerBDMA0
ldr pc,=HandlerBDMA1
ldr pc,=HandlerWDT
ldr pc,=HandlerUERR01 ; 0x54
b.
b.
ldr pc,=HandlerTIMER0 ; 0x60
ldr pc,=HandlerTIMER1
ldr pc,=HandlerTIMER2
ldr pc,=HandlerTIMER3
ldr pc,=HandlerTIMER4
ldr pc,=HandlerTIMER5 ; 0x74
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b.
b.
ldr pc,=HandlerURXD0 ; 0x80
ldr pc,=HandlerURXD1
ldr pc,=HandlerIIC
ldr pc,=HandlerSIO
ldr pc,=HandlerUTXD0
ldr pc,=HandlerUTXD1 ; 0x94
b.
b.
ldr pc,=HandlerRTC ; 0xa0
b.
b.
b.
b.
b.
b.
ldr pc,=HandlerADC ; 0xb4
5. Interrupt Controller Special Registers
1) Interrupt Control Register (INTCON)
Table 4-21 Interrupt Control Registers
Table 4-21 Interrupt Control Register Bit Description
NOTE: FIQ interrupt mode does not support vectored interrupt mode.
2) Interrupt Pending Register (INTPND)
Each of the 26 bits in the interrupt pending register, INTPND, corresponds to an interrupt source. When an
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interrupt request is generated, the corresponding interrupt bit in INTPND will be set to 1. The interrupt service
routine must then clear the pending condition by writing '1' to the corresponding bit of I_ISPC/F_ISPC. When
several interrupt sources generate requests simultaneously, the INTPND will indicate all interrupt sources that
have generated an interrupt request. Even if the interrupt source is masked by INTMSK, the corresponding
pending bit can be set to 1.
Table 4-23 Interrupt Pending Register
3) Interrupt Mode Register (INTMOD)
Each of the 26 bits in the interrupt mode register, INTMOD, corresponds to an interrupt source. When the
interrupt mode bit for one source is set to 1, the ARM7TDMI core will process the interrupt in the FIQ (fast
interrupt) mode. Otherwise, the interrupt is processed in the IRQ mode (normal interrupt). The 26-interrupt
sources are summarized as follows:
Table 4-24 Interrupt Mode Register
4) Interrupt Mask Register (INTMSK)
Each of the 26 bits except the global mask bit in the interrupt mask register, INTMSK, corresponds to an
interrupt source.
Table 4-25 Interrupt Mask Register
If the INTMSK is changed in ISR (interrupt service routine) and the vectored interrupt is used, an INTMSK bit
cannot mask an interrupt event, which had been latched in INTPND before the INTMSK bit was set. To
eliminate this problem, clear the corresponding pending bit (INTPND) after changing INTMSK.
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5) IRQ Vectored Mode Register
Table 4-26 IRQ Vectored Mode Register
NOTE: In FIQ mode, there is no service pending register like I_ISPR, users must check INTPND register.
The priority-generating block consists of five units, 1 master unit and 4 slave units. Each slave
priority-generating unit manages six interrupt sources. The master priority-generating unit manages 4 slave
units and 2 interrupt sources. Each slave unit has 4 programmable priority source (sGn) and 2 fixed priority
sources (kn). The priority among the 4 sources in each slave unit is determined by the I_PSLV register. The
other 2 fixed priorities have the lowest priority among the 6 sources. The master priority-generating unit
determines the priority between 4 slave units and 2 interrupt sources using the I_PMST register. The 2 interrupt
sources, INT_RTC and INT_ADC, have the lowest priority among the 26 interrupt sources. If several interrupts
are requested at the same time, the I_ISPR register shows only the requested interrupt source with the highest
priority.
6) IRQ/FIQ Interrupt Service Pending Clear Register (I_ISPC/F_ISPC)
I_ISPC/F_ISPC clears the interrupt pending bit (INTPND). I_ISPC/F_ISPC also informs the interrupt controller
of the end of corresponding ISR (interrupt service routine). At the end of ISR (interrupt service routine), the
corresponding pending bit must be cleared.
A bit of INTPND is clear to zero by writing ‘1’ on I_ISPC/F_ISPC. This feature reduces the code size to clear
the INTPND.
NOTE: to clear the I_ISPC/F_ISPC, the following two rules has to be obeyed:
• The I_ISPC/F_ISPC registers are accessed only once in ISR
• The pending bit in I_ISPR/INTPND register should be cleared by writing I_ISPC register.
Table 4-27 IRQ/FIQ Interrupt Service Pending Clear Register
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6. Circuit Description
As shown in Figure 4-6, the external interrupts EXINT6 and EXINT7 are used in this Lab. The button SB2 and
SB3 generate interrupts. When the buttons are pressed, EXINT6 and EXINT7 are connected to the ground and a
0V signal is present at these pins. This will initiate an interrupt request. After the CPU accepts the requests, the
corresponded ISRs are executed to implement LED1 and LED2 display. From the presentation of the interrupt
functionality, the EXINT6 and EXINT7 are using the same interrupt controller. As a result, the CPU will only
accept one interrupt request at one time. In another word, when SB2 is pressed, the CPU will not process the
EXINT7 interrupt routine that was generated by pressing SB7 until the EXINT6 interrupt routine is processed.
Please note this functionality in the operation of the Lab.
The 8-SEG LED display circuit is not given here. If needed, please refer to the “8-SEG LED Display Lab”
presented in Section 4.6.
LED1
23 R95
NGCS4
24 R96
NGCS5
LED2
VDD33 47
S3C44B0X
R111 SB2
EXINT6 1 3
2 4
R112 SB3
EXINT7 1 3
2 4
GND
Figure 4-6 Interrupt Circuit
4.3.5 Operation Steps
1) Prepare the Lab environment. Connect the Embest Emulator to the target board and turn-on the power supply
of the target board.
2) Open the ExInt4567.ews project file that is located in
the …\EmbestIDE\Examples\Samsung\S3CEV40\ExInt4567 directory. Compile and link the project, connect to
the target board and download the program. Please note that the ..\common\ev40boot.cs must be used as a
command file to configure the memory before the download can take place.
3) Select ViewÆDebug WindowsÆRegister (or press Alt+5). In the Register window, select peripheral register
(Peripheral). Open the INTERRUPT registers, watch the value changes in the INTPND and I_ISPR registers as
shown in Figure 4-7.
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Figure 4-7 IDE Peripheral Register Window
4) Set a break point at the entry point of Eint4567Isr.c as shown in Figure 4-8. Execute the program; press SB2
or SB3, the program will stop at the break point. Double click the INTPND and I_ISPR; the register window
will be open. Watch the value changes in these registers. Watch the value change at bit21 before and after the
program executed.
Figure 4-8 At the Interrupt Time
5) Cancel all of the above break points. Set a break point at main() function shown in Figure 4-9. Execute the
program. When the program will stop at the break point, watch the value changes at bit21 of these two registers
again. Through these operations, understand the functions of INTPND and I_ISPR register in the interrupt
processing.
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Figure 4-9 After Interrupt Finished
6) Cancel all the above break points. Execute the program, press SB2 or SB3. Watch the changes of LED1,
LED2 and 8-SEG LED on the target board.
(7) After understanding and leaning the Lab, do the exercises at the end of the Lab.
1. Environment Initialization Code
.macro HANDLER HandleLabel
sub sp,sp,#4 /* decrement sp(to store jump address) */
stmfd sp!,{r0} /* PUSH the work register to stack(lr does't push because it return to original
address) */
ldr r0,=\HandleLabel/* load the address of HandleXXX to r0 */
ldr r0,[r0] /* load the contents(service routine start address) of HandleXXX */
str r0,[sp,#4] /* store the contents(ISR) of HandleXXX to stack */
ldmfd sp!,{r0,pc} /* POP the work register and pc(jump to ISR) */
.endm
ENTRY:
b ResetHandler /* for debug */
b HandlerUndef /* handlerUndef */
b HandlerSWI /* SWI interrupt handler*/
b HandlerPabort /* handlerPAbort */
b HandlerDabort /* handlerDAbort */
b. /* handlerReserved */
b HandlerIRQ
b HandlerFIQ
2. Interrupt Initialization
/*********************************************************************
* name: init_Eint
* func:
* para: none
* ret: none
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* modify:
* comment:
**********************************************************************/
void init_Eint(void)
{
/* enable interrupt */
rI_ISPC = 0x3ffffff;
rEXTINTPND = 0xf; // clear EXTINTPND reg
rINTMOD = 0x0;
rINTCON = 0x1;
rINTMSK = ~(BIT_GLOBAL|BIT_EINT1|BIT_EINT4567);
/* set EINT interrupt handler */
pISR_EINT4567 = (int)Eint4567Isr;
pISR_EINT1 = (int)KeyIsr;
/* PORT G */
rPCONG = 0xffff; // EINT7~0
rPUPG = 0x0; // pull up enable
rEXTINT = rEXTINT|0x22220020; // EINT1¡¢EINT4567 falling edge mode
rI_ISPC |= (BIT_EINT1|BIT_EINT4567);
rEXTINTPND = 0xf; // clear EXTINTPND reg
}
3. Interrupt Service Routine
/**********************************************************************
* name: Eint4567Isr
* func:
* para: none
* ret: none
* modify:
* comment:
************************************************************************/
void Eint4567Isr(void)
{
if(IntNesting)
{
IntNesting++;
Uart_Printf("IntNesting = %d\n",IntNesting);//An Extern Intrrupt had been occur before dealing with
one.
}
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which_int = rEXTINTPND;
rEXTINTPND = 0xf; //clear EXTINTPND reg.
rI_ISPC |= BIT_EINT4567; //clear pending_bit
}
4.3.7 Exercises
(1) Get familiar with the S3C44B0X timer controller, the related registers and the principle of timer interrupt.
(2) Write a program and make usage of timer interrupt to implement LED1 and LED2 flashing every 1s.
4.4 Serial Port Communication Lab
4.4.1 Purpose
● Get familiar with the S3C44B0X UART architecture and principles of serial communication.
● Master ARM processor serial port programming methods.
4.4.2 Lab Equipment
● Hardware: Embest S3CEV40 hardware platform, Embest Standard/Power Emulator, PC.
● Software: Embest IDE 2003, Windows 98/2000/NT/XP operation system.
4.4.3 Content of the Lab
Learn the functions of the S3C44B0X UART related registers. Get familiar with the S3C44B0X UART related
interface. Write a serial port communication program. Monitor the S3CEV40 serial port and return the received
characters.
4.4.4 Principles of the Lab
1. S3C44B0X Serial Communication Unit (UART)
The S3C44B0X UART (Universal Asynchronous Receiver and Transmitter) unit provides two independent
asynchronous serial I/O (SIO) ports, each of which can operate in interrupt-based or DMA-based mode. In other
words, UART can generate an interrupt or DMA request to transfer data between CPU and UART. It can
support bit rates of up to 115.2K bps. Each UART channel contains two 16-byte FIFOs for receive and transmit
data. The S3C44B0X UART includes programmable baud-rates, infra-red (IR) transmit/receive, one or two stop
bit insertion, 5-bit, 6-bit, 7-bit or 8-bit data width and parity checking.
Each UART contains a baud-rate generator, transmitter, receiver and control unit, as shown in Figure 10-1. The
baud-rate generator can be clocked by MCLK. The transmitter and the receiver contain 16-byte FIFOs and data
shifters. Data, which is to be transmitted, is written to FIFO and then copied to the transmit shifter. It is then
shifted out by the transmit data pin (TxDn). The received data is shifted from the received data pin (RxDn), and
then copied to FIFO from the shifter.
UART Operation
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The following sections describe the UART operations that include data transmission, data reception, interrupt
generation, baud-rate generation, loop back mode, infra-red mode, and auto flow control.
Data Transmission
The data frame for transmission is programmable. It consists of a start bit, 5 to 8 data bits, an optional parity bit
and 1 to 2 stop bits, which can be specified by the line control register (UCONn). The transmitter can also
produce the break condition. The break condition forces the serial output to logic 0 state for a duration longer
than one frame transmission time. This block transmit break signal after the present transmission word transmits
perfectly. After the break signal transmit, continuously transmit data into the Tx FIFO (Tx holding register in
the case of Non-FIFO mode).
Data Reception
Like the transmission, the data frame for reception is also programmable. It consists of a start bit, 5 to 8 data bits,
an optional parity bit and 1 to 2 stop bits in the line control register (UCONn). The receiver can detect overrun
error, parity error, frame error and break condition, each of which can set an error flag.
● The overrun error indicates that new data has overwritten the old data before the old data has been read.
● The parity error indicates that the receiver has detected an unexpected parity condition.
● The frame error indicates that the received data does not have a valid stop bit.
● The break condition indicates that the RxDn input is held in the logic 0 state for a duration longer than one
frame transmission time.
Receive time-out condition occurs when it does not receive data during the 3 word time and the Rx FIFO is not
empty in the FIFO mode.
Auto Flow Control (ACF)
S3C44BOXs UART supports auto flow control with nRTS and nCTC signals, in case it would have to connect
UART to UART. If users connect UART to a Modem, disable auto flow control bit in UMCONn registers and
control the signal of nRTS by software.
Baud-Rate Generation
The baud rate divisor register (UBRDIVn) controls the baud rate. The serial Tx/Rx clock rate (baud rate) is
calculated as follows:
UBRDIVn = (round_off)(MCLK / (bps x 16)) -1
The divisor should be from 1 to (216-1). For example, if the baud-rate is 115200 bps and MCLK is 40 MHz,
UBRDIVn is:
UBRDIVn = (int)(40000000 / (115200 x 16)+0.5) -1
= (int)(21.7+0.5) -1
= 22 -1 = 21
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PUPC access address: 0X01D20018
PCONC reset value: 0X0FF0FFFF
Table 4-15 Port D
Port D Pin function Port D Pin function Port D Pin function
PD0 VD0 PD3 VD3 PD6 VM
PD1 VD1 PD4 VCLK PD7 VFRAME
PD2 VD2 PD5 VLINE
PCOND access address: 0X01D2001C
PDATD access address: 0X01D20020
PUPD access address: 0X01D20024
PCOND reset value: 0XAAAA
Table 4-16 Port E
Port E Pin function Port E Pin function Port E Pin function
PE0 OUTPUT(LCD) PE3 RESERVE PE6 OUTPUT(TSP)
PE1 TXD0 PE4 OUTPUT(TSP) PE7 OUTPUT(TSP)
PE2 RXD0 PE5 OUTPUT(TSP) PE8 CODECLK
PCONE access address: 0X01D20028
PDATE access address: 0X01D2002C
PUPE access address: 0X01D20030
PCONE reset value: 0X25529
Table 4-17 Port F
Port F Pin function Port F Pin function Port F Pin function
PF0 IICSCL PF3 IN(Nand Flash) PF6 out(Nand Flash)
PF1 IICSDA PF4 out(Nand Flash) PF7 IN(bootloader)
PF2 RESERVED PF5 out(Nand Flash) PF8 IN(bootloader)
PCONF access address: 0X01D20034
PDATF access address: 0X01D20038
PUPF access address: 0X01D2003C
PCONF reset value: 0X00252A
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Table 4-18 Port G
Port G Pin function Port G Pin function Port G Pin function
PG0 EXINT0 PG3 EXINT3 PG6 EXINT6
PG1 EXINT1 PG4 EXINT4 PG7 EXINT7
PG2 EXINT2 PG5 EXINT5
PCONG access address: 0X01D20040
PDATG access address: 0X01D20044
PUPG access address: 0X01D20048
PCONG reset value: 0XFFFF
2. The Description of the Circuit
In Table 4-13 PB9 and PB10 pins are defined as outputs and are connected to LED1 and LED2. Figure 4-5
shows the circuit connections for the LED1 and LED2. The anodes of LED1 and LED2 are connected to the pin
47 of S3C44B0X which is VDD33. VDD33 pin provides a 3.3V dc voltage. The cathodes of LED1 and LED2
are connected to pin 23 (PB9) and 24 (PB10), respectively. These two pins belong to Port B and have been
configured as outputs. Writing a 1 or a 0 to the specific bit of the PDATAB register can make the pin’s output
low or high. When the pin 23, 24 is low, the LEDs will be on (lit). When the pin 23, 24 is high, the LEDs will be
off.
LED1
23 R95
NGCS4
24 R96
NGCS5
S3C44B0X LED2
47
VDD33
Figure 4-5. Connection diagram to LED 1 and LED 2
4.2.5 Operation Steps
1) Prepare the Lab environment. Connect the Embest Emulator to the target board. Connect the target board
UART0 to the PC serial port through the serial cable provided by the Embest development system.
2) Run the PC Hyper Terminal (set to 115200 bits per second, 8 data bits, none parity, 1 stop bits, none flow
control).
3) Connect the Embest Emulator to the target board. Open the LED_test.ews project file that is located in
the …\EmbestIDE\Examples\Samsung\S3CEV40 directory. Compile and link the project. Connect to the target
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board and download the program.
NOTE: please note that the debug window should be set as in Figure 4-5a:
Figure 4-5a. Debug settings for the project
4) Watch the hyper terminal output. The following should be displayed:
Embest 44B0X Evaluation Board (S3CEV40)
LED Test Example
5) The LED1 and LED2 will be in the following states:
LED1 on Æ LED2 on Æ LED1 and LED2 onÆ LED2 off Æ LED1 off.
4.2.6 Sample Programs
/*****************************************************************************
* File Name: light.c
* Author: embest
* Description: control board's two LEDs on or offf
* History:
*****************************************************************************/
/*--- include files ---*/
#include "44b.h"
#include "44blib.h"
/*--- global variables ---*/
int led_state; /* LED status */
/*--- function declare ---*/
void Led_Test(); /* LED test */
void leds_on(); /* all leds on */
void leds_off(); /* all leds off */
void led1_on(); /* led 1 on */
void led1_off(); /* led 1 off */
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void led2_on(); /* led 2 on */
void led2_off(); /* led 2 off */
//void Led_Display(int LedStatus); /* led control */
/*--- function code---*/
/*************************************************************************
* name: Led_Test
* func: leds test funciton
* para: none
* ret: none
* modify:
* comment:
**************************************************************************/
void Led_Test()
{
/* 1 on -> 2 on -> all on -> 2 off -> 1 off */
leds_off();
Delay(1000);
led1_on();
Delay(1000);
led1_off();
led2_on();
Delay(1000);
leds_on();
Delay(1000);
led2_off();
Delay(1000);
led1_off();
}
/***************************************************************************
* name: leds_on
* func: all leds on
* para: none
* ret: none
* modify:
* comment:
***************************************************************************/
void leds_on()
{
Led_Display(0x3);
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}
/**************************************************************************
* name: leds_off
* func: all leds off
* para: none
* ret: none
* modify:
* comment:
*****************************************************************************/
void leds_off()
{
Led_Display(0x0);
}
/****************************************************************************
* name: led1_on
* func: led 1 on
* para: none
* ret: none
* modify:
* comment:
*****************************************************************************/
void led1_on()
{
led_state = led_state | 0x1;
Led_Display(led_state);
}
/*****************************************************************************
* name: led1_off
* func: led 1 off
* para: none
* ret: none
* modify:
* comment:
****************************************************************************/
void led1_off()
{
led_state = led_state & 0xfe;
Led_Display(led_state);
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}
/*****************************************************************************
* name: led2_on
* func: led 2 on
* para: none
* ret: none
* modify:
* comment:
******************************************************************************/
void led2_on()
{
led_state = led_state | 0x2;
Led_Display(led_state);
}
/*****************************************************************************
* name: led2_off
* func: led 2 off
* para: none
* ret: none
* modify:
* comment:
******************************************************************************/
void led2_off()
{
led_state = led_state & 0xfd;
Led_Display(led_state);
}
#define _LIB_LED_off // _LIB_LED_off -- don't use LIB settings.
#ifndef _LIB_LED_off
/**************************************************************************
* name: Led_Display
* func: Led Display control function
* para: LedStatus -- led's status
* ret: none
* modify:
* comment:
**************************************************************************/
void Led_Display(int LedStatus)
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{
led_state = LedStatus;
if((LedStatus&0x01)==0x01)
rPDATB=rPDATB&0x5ff;
else
rPDATB=rPDATB|0x200;
if((LedStatus&0x02)==0x02)
rPDATB=rPDATB&0x3ff;
else
rPDATB=rPDATB|0x400;
}
#endif
4.2.7 Exercises
Write a program to implement LED1 and LED2 display 00-11 in a loop.
4.3 Interrupt Lab
4.3.1 Purpose
● Get familiar with ARM interrupt methods and principles.
● Get familiar with the details of ISR (Interrupt Service Routine) programming in ARM based systems.
4.3.2 Lab Equipment
● Hardware: Embest S3CEV40 hardware platform, Embest Standard/Power Emulator, PC.
● Software: Embest IDE 2003, Windows 98/2000/NT/XP operation system.
4.3.3 Content of the Lab
Learn the principals of ARM interrupt system. Get familiar with S3C44B0X interrupt registers. Learn various
programming methods used in dealing with interrupts. Write programs that implement an interrupt service
routine.
● Use button SB2 to trigger the interrupt EINT6. The interrupt will turn LED1 on; then the 8-SEG LED will
display the characters 0 to F 1 time; then the LED1 will be turned off.
● Use button SB3 to trigger the interrupt EINT7. The interrupt will turn LED1 on; then the 8-SEG LED will
display the characters 0 to F 1 time; then the LED1 will be turned off.
To understand the interface to the 8-SEG LED display please refer to the “8-SEG LED Display Lab” presented
in Section 4.6.
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4.3.4 Principles of the Lab
The integrated interrupt controller of the S3C44B0X processor can process 30 interrupt requests. These
interrupt sources include internal peripherals such as the DMA controller, UART, SIO, etc. In these interrupt
sources, the four external interrupts (EINT4/5/6/7) are 'OR'ed to the interrupt controller.The UART0 and 1
Error interrupt are 'OR'ed, as well.
The role of the interrupt controller is to ask for the FIQ or IRQ interrupt request to the ARM7TDMI core after
making the arbitration process when there are multiple interrupt requests from internal peripherals and external
interrupt request pins.
Originally, ARM7TDMI core permits only the FIQ or IRQ interrupt, which is the arbitration process based on
priority by software. For example, if you define all interrupt sources as IRQ (Interrupt Mode Setting), and, if
there are 10 interrupt requests at the same time, you can determine the interrupt service priority by reading the
interrupt pending register, which indicates the type of interrupt request that will occur.
This kind of interrupt process requires a long interrupt latency until to jump to the exact service routine. (The
S3C44B0X may support this kind of interrupt processing.) To reduce the interrupt latency, S3C44B0X
microcontroller supports a new interrupt processing called vectored interrupt mode, which is a general feature
of the CISC type microcontrollers. To accomplish this, the hardware inside the S3C44B0X interrupt controller
provides the interrupt service vector directly.
When the multiple interrupt request sources are present, the hardware priority logic determines which interrupt
should be serviced. At the same time, this hardware logic applies the jump instruction of the vector table to 0x18
(or 0x1c), which performs the jump to the corresponding service routine. Compared with the previous software
method, it will reduce the interrupt latency, dramatically.
1. Interrupt Controller Operation
1) F-bit and I-bit of PSR (program status register)
If the F-bit of PSR (program status register in ARM7TDMI CPU) is set to 1, the CPU does not accept the FIQ
(fast interrupt request) from the interrupt controller. If I-bit of PSR (program status register in ARM7TDMI
CPU) is set to 1, the CPU does not accept the IRQ (interrupt request) from the interrupt controller. So, to enable
the interrupt reception, the F-bit or I-bit of PSR has to be cleared to 0 and also the corresponding bit of INTMSK
has to be cleared to 0.
2) Interrupt Mode
ARM7TDMI has 2 types of interrupt mode, FIQ or IRQ. All the interrupt sources determine the mode of
interrupt to be used at interrupt request.
3) Interrupt Pending Register
Indicates whether or not an interrupt request is pending. Whenever a pending bit is set, the interrupt service
routine starts if the I-flag or F-flag is cleared to 0. The Interrupt Pending Register is a read-only register, so the
service routine must clear the pending condition by writing a 1 to I_ISPC or F_ISPC.
4) Interrupt Mask Register
Indicates that an interrupt has been disabled if the corresponding mask bit is 1. If an interrupt mask bit of
INTMSK is 0, the interrupt will be serviced normally. If the corresponding mask bit is 1 and the interrupt is
generated, the pending bit will be set. If the global mask bit is set to 1, the interrupt pending bit will be set but all
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interrupts will not be serviced.
2. Interrupt Sources
Among 30 interrupt sources, 26 sources are provided for the interrupt controller. Four external interrupt
(EINT4/5/6/7) requests are ORed to provide a single interrupt source to the interrupt controller, and two UART
error interrupts (UERROR0/1) use the ORed configuration.
NOTE: EINT4/5/6/7 share the same interrupt request line. Therefore, the ISR (interrupt service routine) will
discriminate these four interrupt sources by reading the EXTINPHD[3:0] register. EXTINPND[3:0] must be
cleared by writing a 1 in the ISR after the corresponding ISR has been completed.
Table 4-19.
3. Vectored Interrupt Mode (Only for IRQ)
S3C44B0X has a new feature, the vectored interrupt mode, in order to reduce the interrupt latency time.
When the ARM7TDMI core receives the IRQ interrupt request from the interrupt controller, ARM7TDMI
executes the instruction located at address 0x00000018. In vectored interrupt mode, the interrupt controller will
load branch instructions on the data bus when ARM7TDMI fetches the instructions at 0x00000018. The branch
instructions let the program counter be a unique address corresponding to each interrupt source.
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The interrupt controller generates the machine code for branching to the vector address of each interrupt source.
For example, if EINT0 is IRQ, the interrupt controller must generate the branch instruction which branches to
0x20 instead of 0x18. As a result, the interrupt controller generates the machine code, 0xea000000.
The user program code must locate the branch instruction, which branches to the corresponding ISR (interrupt
service routine) at each vector address. The machine code, branch instruction, at the corresponding vector
address is calculated as follows:
Branch Instruction machine code for vectored interrupt mode = 0xea000000 +((
Note: A relative address must be calculated for the branch instruction.
Table 4-20 The Vector Addresses of Interrupt Sources
For example, if Timer 0 interrupt is to be processed in vector interrupt mode, the branch instruction, which
jumps to the ISR, is located at 0x00000060. The ISR start address is 0x10000. The following 32bit machine
code is written at 0x00000060. The machine code at 0x00000060 is:
0xea000000+((0x10000-0x60-0x8)>>2) = 0xea000000+0x3fe6 = 0xea003fe6
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The assembler usually generates the machine code automatically and therefore the machine code does not have
to be calculated as above.
4. Example of Vectored Interrupt Mode
In the vectored interrupt mode, CPU will branch to each interrupt address when an interrupt request is generated.
As a result, at the corresponding interrupt address there must be a branch instruction that jumps to the
corresponding ISR:
ENTRY
b ResetHandler ; 0x00
b HandlerUndef ; 0x04
b HandlerSWI ; 0x08
b HandlerPabort ; 0x0c
b HandlerDabort ; 0x10
b . ; 0x14
b HandlerIRQ ; 0x18
b HandlerFIQ ; 0x1c
ldr pc,=HandlerEINT0 ; 0x20
ldr pc,=HandlerEINT1
ldr pc,=HandlerEINT2
ldr pc,=HandlerEINT3
ldr pc,=HandlerEINT4567
ldr pc,=HandlerTICK ; 0x34
b.
b.
ldr pc,=HandlerZDMA0 ; 0x40
ldr pc,=HandlerZDMA1
ldr pc,=HandlerBDMA0
ldr pc,=HandlerBDMA1
ldr pc,=HandlerWDT
ldr pc,=HandlerUERR01 ; 0x54
b.
b.
ldr pc,=HandlerTIMER0 ; 0x60
ldr pc,=HandlerTIMER1
ldr pc,=HandlerTIMER2
ldr pc,=HandlerTIMER3
ldr pc,=HandlerTIMER4
ldr pc,=HandlerTIMER5 ; 0x74
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b.
b.
ldr pc,=HandlerURXD0 ; 0x80
ldr pc,=HandlerURXD1
ldr pc,=HandlerIIC
ldr pc,=HandlerSIO
ldr pc,=HandlerUTXD0
ldr pc,=HandlerUTXD1 ; 0x94
b.
b.
ldr pc,=HandlerRTC ; 0xa0
b.
b.
b.
b.
b.
b.
ldr pc,=HandlerADC ; 0xb4
5. Interrupt Controller Special Registers
1) Interrupt Control Register (INTCON)
Table 4-21 Interrupt Control Registers
Table 4-21 Interrupt Control Register Bit Description
NOTE: FIQ interrupt mode does not support vectored interrupt mode.
2) Interrupt Pending Register (INTPND)
Each of the 26 bits in the interrupt pending register, INTPND, corresponds to an interrupt source. When an
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interrupt request is generated, the corresponding interrupt bit in INTPND will be set to 1. The interrupt service
routine must then clear the pending condition by writing '1' to the corresponding bit of I_ISPC/F_ISPC. When
several interrupt sources generate requests simultaneously, the INTPND will indicate all interrupt sources that
have generated an interrupt request. Even if the interrupt source is masked by INTMSK, the corresponding
pending bit can be set to 1.
Table 4-23 Interrupt Pending Register
3) Interrupt Mode Register (INTMOD)
Each of the 26 bits in the interrupt mode register, INTMOD, corresponds to an interrupt source. When the
interrupt mode bit for one source is set to 1, the ARM7TDMI core will process the interrupt in the FIQ (fast
interrupt) mode. Otherwise, the interrupt is processed in the IRQ mode (normal interrupt). The 26-interrupt
sources are summarized as follows:
Table 4-24 Interrupt Mode Register
4) Interrupt Mask Register (INTMSK)
Each of the 26 bits except the global mask bit in the interrupt mask register, INTMSK, corresponds to an
interrupt source.
Table 4-25 Interrupt Mask Register
If the INTMSK is changed in ISR (interrupt service routine) and the vectored interrupt is used, an INTMSK bit
cannot mask an interrupt event, which had been latched in INTPND before the INTMSK bit was set. To
eliminate this problem, clear the corresponding pending bit (INTPND) after changing INTMSK.
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5) IRQ Vectored Mode Register
Table 4-26 IRQ Vectored Mode Register
NOTE: In FIQ mode, there is no service pending register like I_ISPR, users must check INTPND register.
The priority-generating block consists of five units, 1 master unit and 4 slave units. Each slave
priority-generating unit manages six interrupt sources. The master priority-generating unit manages 4 slave
units and 2 interrupt sources. Each slave unit has 4 programmable priority source (sGn) and 2 fixed priority
sources (kn). The priority among the 4 sources in each slave unit is determined by the I_PSLV register. The
other 2 fixed priorities have the lowest priority among the 6 sources. The master priority-generating unit
determines the priority between 4 slave units and 2 interrupt sources using the I_PMST register. The 2 interrupt
sources, INT_RTC and INT_ADC, have the lowest priority among the 26 interrupt sources. If several interrupts
are requested at the same time, the I_ISPR register shows only the requested interrupt source with the highest
priority.
6) IRQ/FIQ Interrupt Service Pending Clear Register (I_ISPC/F_ISPC)
I_ISPC/F_ISPC clears the interrupt pending bit (INTPND). I_ISPC/F_ISPC also informs the interrupt controller
of the end of corresponding ISR (interrupt service routine). At the end of ISR (interrupt service routine), the
corresponding pending bit must be cleared.
A bit of INTPND is clear to zero by writing ‘1’ on I_ISPC/F_ISPC. This feature reduces the code size to clear
the INTPND.
NOTE: to clear the I_ISPC/F_ISPC, the following two rules has to be obeyed:
• The I_ISPC/F_ISPC registers are accessed only once in ISR
• The pending bit in I_ISPR/INTPND register should be cleared by writing I_ISPC register.
Table 4-27 IRQ/FIQ Interrupt Service Pending Clear Register
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6. Circuit Description
As shown in Figure 4-6, the external interrupts EXINT6 and EXINT7 are used in this Lab. The button SB2 and
SB3 generate interrupts. When the buttons are pressed, EXINT6 and EXINT7 are connected to the ground and a
0V signal is present at these pins. This will initiate an interrupt request. After the CPU accepts the requests, the
corresponded ISRs are executed to implement LED1 and LED2 display. From the presentation of the interrupt
functionality, the EXINT6 and EXINT7 are using the same interrupt controller. As a result, the CPU will only
accept one interrupt request at one time. In another word, when SB2 is pressed, the CPU will not process the
EXINT7 interrupt routine that was generated by pressing SB7 until the EXINT6 interrupt routine is processed.
Please note this functionality in the operation of the Lab.
The 8-SEG LED display circuit is not given here. If needed, please refer to the “8-SEG LED Display Lab”
presented in Section 4.6.
LED1
23 R95
NGCS4
24 R96
NGCS5
LED2
VDD33 47
S3C44B0X
R111 SB2
EXINT6 1 3
2 4
R112 SB3
EXINT7 1 3
2 4
GND
Figure 4-6 Interrupt Circuit
4.3.5 Operation Steps
1) Prepare the Lab environment. Connect the Embest Emulator to the target board and turn-on the power supply
of the target board.
2) Open the ExInt4567.ews project file that is located in
the …\EmbestIDE\Examples\Samsung\S3CEV40\ExInt4567 directory. Compile and link the project, connect to
the target board and download the program. Please note that the ..\common\ev40boot.cs must be used as a
command file to configure the memory before the download can take place.
3) Select ViewÆDebug WindowsÆRegister (or press Alt+5). In the Register window, select peripheral register
(Peripheral). Open the INTERRUPT registers, watch the value changes in the INTPND and I_ISPR registers as
shown in Figure 4-7.
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Figure 4-7 IDE Peripheral Register Window
4) Set a break point at the entry point of Eint4567Isr.c as shown in Figure 4-8. Execute the program; press SB2
or SB3, the program will stop at the break point. Double click the INTPND and I_ISPR; the register window
will be open. Watch the value changes in these registers. Watch the value change at bit21 before and after the
program executed.
Figure 4-8 At the Interrupt Time
5) Cancel all of the above break points. Set a break point at main() function shown in Figure 4-9. Execute the
program. When the program will stop at the break point, watch the value changes at bit21 of these two registers
again. Through these operations, understand the functions of INTPND and I_ISPR register in the interrupt
processing.
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Figure 4-9 After Interrupt Finished
6) Cancel all the above break points. Execute the program, press SB2 or SB3. Watch the changes of LED1,
LED2 and 8-SEG LED on the target board.
(7) After understanding and leaning the Lab, do the exercises at the end of the Lab.
1. Environment Initialization Code
.macro HANDLER HandleLabel
sub sp,sp,#4 /* decrement sp(to store jump address) */
stmfd sp!,{r0} /* PUSH the work register to stack(lr does't push because it return to original
address) */
ldr r0,=\HandleLabel/* load the address of HandleXXX to r0 */
ldr r0,[r0] /* load the contents(service routine start address) of HandleXXX */
str r0,[sp,#4] /* store the contents(ISR) of HandleXXX to stack */
ldmfd sp!,{r0,pc} /* POP the work register and pc(jump to ISR) */
.endm
ENTRY:
b ResetHandler /* for debug */
b HandlerUndef /* handlerUndef */
b HandlerSWI /* SWI interrupt handler*/
b HandlerPabort /* handlerPAbort */
b HandlerDabort /* handlerDAbort */
b. /* handlerReserved */
b HandlerIRQ
b HandlerFIQ
2. Interrupt Initialization
/*********************************************************************
* name: init_Eint
* func:
* para: none
* ret: none
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* modify:
* comment:
**********************************************************************/
void init_Eint(void)
{
/* enable interrupt */
rI_ISPC = 0x3ffffff;
rEXTINTPND = 0xf; // clear EXTINTPND reg
rINTMOD = 0x0;
rINTCON = 0x1;
rINTMSK = ~(BIT_GLOBAL|BIT_EINT1|BIT_EINT4567);
/* set EINT interrupt handler */
pISR_EINT4567 = (int)Eint4567Isr;
pISR_EINT1 = (int)KeyIsr;
/* PORT G */
rPCONG = 0xffff; // EINT7~0
rPUPG = 0x0; // pull up enable
rEXTINT = rEXTINT|0x22220020; // EINT1¡¢EINT4567 falling edge mode
rI_ISPC |= (BIT_EINT1|BIT_EINT4567);
rEXTINTPND = 0xf; // clear EXTINTPND reg
}
3. Interrupt Service Routine
/**********************************************************************
* name: Eint4567Isr
* func:
* para: none
* ret: none
* modify:
* comment:
************************************************************************/
void Eint4567Isr(void)
{
if(IntNesting)
{
IntNesting++;
Uart_Printf("IntNesting = %d\n",IntNesting);//An Extern Intrrupt had been occur before dealing with
one.
}
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Embedded Systems Development and Labs; The English Edition
which_int = rEXTINTPND;
rEXTINTPND = 0xf; //clear EXTINTPND reg.
rI_ISPC |= BIT_EINT4567; //clear pending_bit
}
4.3.7 Exercises
(1) Get familiar with the S3C44B0X timer controller, the related registers and the principle of timer interrupt.
(2) Write a program and make usage of timer interrupt to implement LED1 and LED2 flashing every 1s.
4.4 Serial Port Communication Lab
4.4.1 Purpose
● Get familiar with the S3C44B0X UART architecture and principles of serial communication.
● Master ARM processor serial port programming methods.
4.4.2 Lab Equipment
● Hardware: Embest S3CEV40 hardware platform, Embest Standard/Power Emulator, PC.
● Software: Embest IDE 2003, Windows 98/2000/NT/XP operation system.
4.4.3 Content of the Lab
Learn the functions of the S3C44B0X UART related registers. Get familiar with the S3C44B0X UART related
interface. Write a serial port communication program. Monitor the S3CEV40 serial port and return the received
characters.
4.4.4 Principles of the Lab
1. S3C44B0X Serial Communication Unit (UART)
The S3C44B0X UART (Universal Asynchronous Receiver and Transmitter) unit provides two independent
asynchronous serial I/O (SIO) ports, each of which can operate in interrupt-based or DMA-based mode. In other
words, UART can generate an interrupt or DMA request to transfer data between CPU and UART. It can
support bit rates of up to 115.2K bps. Each UART channel contains two 16-byte FIFOs for receive and transmit
data. The S3C44B0X UART includes programmable baud-rates, infra-red (IR) transmit/receive, one or two stop
bit insertion, 5-bit, 6-bit, 7-bit or 8-bit data width and parity checking.
Each UART contains a baud-rate generator, transmitter, receiver and control unit, as shown in Figure 10-1. The
baud-rate generator can be clocked by MCLK. The transmitter and the receiver contain 16-byte FIFOs and data
shifters. Data, which is to be transmitted, is written to FIFO and then copied to the transmit shifter. It is then
shifted out by the transmit data pin (TxDn). The received data is shifted from the received data pin (RxDn), and
then copied to FIFO from the shifter.
UART Operation
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Embedded Systems Development and Labs; The English Edition
The following sections describe the UART operations that include data transmission, data reception, interrupt
generation, baud-rate generation, loop back mode, infra-red mode, and auto flow control.
Data Transmission
The data frame for transmission is programmable. It consists of a start bit, 5 to 8 data bits, an optional parity bit
and 1 to 2 stop bits, which can be specified by the line control register (UCONn). The transmitter can also
produce the break condition. The break condition forces the serial output to logic 0 state for a duration longer
than one frame transmission time. This block transmit break signal after the present transmission word transmits
perfectly. After the break signal transmit, continuously transmit data into the Tx FIFO (Tx holding register in
the case of Non-FIFO mode).
Data Reception
Like the transmission, the data frame for reception is also programmable. It consists of a start bit, 5 to 8 data bits,
an optional parity bit and 1 to 2 stop bits in the line control register (UCONn). The receiver can detect overrun
error, parity error, frame error and break condition, each of which can set an error flag.
● The overrun error indicates that new data has overwritten the old data before the old data has been read.
● The parity error indicates that the receiver has detected an unexpected parity condition.
● The frame error indicates that the received data does not have a valid stop bit.
● The break condition indicates that the RxDn input is held in the logic 0 state for a duration longer than one
frame transmission time.
Receive time-out condition occurs when it does not receive data during the 3 word time and the Rx FIFO is not
empty in the FIFO mode.
Auto Flow Control (ACF)
S3C44BOXs UART supports auto flow control with nRTS and nCTC signals, in case it would have to connect
UART to UART. If users connect UART to a Modem, disable auto flow control bit in UMCONn registers and
control the signal of nRTS by software.
Baud-Rate Generation
The baud rate divisor register (UBRDIVn) controls the baud rate. The serial Tx/Rx clock rate (baud rate) is
calculated as follows:
UBRDIVn = (round_off)(MCLK / (bps x 16)) -1
The divisor should be from 1 to (216-1). For example, if the baud-rate is 115200 bps and MCLK is 40 MHz,
UBRDIVn is:
UBRDIVn = (int)(40000000 / (115200 x 16)+0.5) -1
= (int)(21.7+0.5) -1
= 22 -1 = 21
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